The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor device require design features of 0.25 microns and under, such as under 0.18 microns, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor methodology.
As device features continually shrink in size, it becomes necessary to decrease the depth of the source and drain regions in the semiconductor substrate, i.e., the junction depth. For example, in forming a polycrystalline silicon gate having a width of about 0.25 microns, the junction depth (X.sub.J) should be no greater than about 800 .ANG.. This objective is extremely difficult to achieve, particularly when implanting boron ions to form P-type source/drain regions.
Boron is conventionally ion implanted at an implantation energy selected to determine the eventual junction depth (X.sub.J) The particular implantation dosage is selected to control the concentration of the resulting source/drain regions. As boron is an extremely light element, it must be implanted at a very low energy in order to achieve a shallow X.sub.J. Accordingly, boron is typically implanted at an energy of about 5 KeV.
It has been found, however, that during annealing to activate the implanted dopants, boron diffusion into the crystalline silicon layer proceeds apace, such that the junction depth of the boron exceeds the targeted maximum depth of about 800 .ANG.. The problem of undefined dopant X.sub.J is believed to stem from various factors. For example, when boron is implanted into a monocrystalline silicon layer, interstitial atoms of silicon are generated, i.e., silicon atoms are displaced from the monocrystalline lattice. A high temperature anneal, known as the dopant activation anneal, is performed to diffuse boron into the monocrystalline silicon lattice. However, during the dopant activation anneal, boron diffuses by transient enhanced diffusion via the interstitial silicon atoms causing a very rapid diffusion into the monocrystalline silicon layer, even though implanted at a very low energy of about 5 KeV. Consequently the resulting dopant profile of boron, after the activation anneal, extends to about 2000 .ANG. or more, which is considerably beyond the targeted maximum of about 800 .ANG.. In copending application Ser. No. 08/726,113, a method is disclosed to minimize boron diffusion during the high temperature activation anneal by initially forming an amorphous region in which boron is ion implanted and then performing a relatively low temperature activation anneal. During the low temperature activation anneal, the amorphous region is crystallized. In copending application Ser. No. 08/992,629, an improvement in the amorphization technique is disclosed, wherein a sub-surface amorphous region is formed to minimize end-of-range defects upon crystallization.
Conventional methodology comprises ion implanting impurities into a semiconductor substrate, using the gate electrode as a mask, to form lightly doped implants. An insulating sidewall spacer is then formed on the side surfaces of the gate electrode, whereby the semiconductor substrate is exposed. A thin thermal oxide screen layer is then grown on the exposed semiconductor surface prior to ion implanting to form moderately or heavily doped implants, followed by a high temperature activation anneal. The thermal oxide screen layer reduces damage to the silicon substrate during moderate or heavy impurity implantation. However, the thermal oxide screen is formed at an elevated temperature, e.g., about 900.degree. C., thereby causing diffusion of the lightly doped implants. Moreover, the high temperature thermal oxidation and attendant stresses induce crystalline defects in the underlying semiconductor substrate. During the high temperature activation anneal, the lightly doped implants rapidly diffuse via the crystalline defects, such as interstitials, by transient enhanced diffusion, thereby significantly increasing the X.sub.J beyond the targeted maximum of about 800 .ANG.. Accordingly, there exists a need for semiconductor methodology in forming CMOS devices having shallow junction depths.